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| Corporation SIGNAL PROCESSING EXCELLENCE SP7512 and HS3120 Double-Buffered 12-Bit Multiplying DAC s s s s s s s Monolithic Construction 12-Bit Resolution 0.01% Non-Linearity Four-Quadrant Multiplication Latch-up Protected Low Power - 30mW Single +15V Power Supply DESCRIPTION... The SP7512 and HS3120 are precision 12-bit multiplying DACs, double-buffered for easy interfacing with microprocessor busses. Both unipolar and bipolar operation can be accommodated with a minimum of external components. The SP7512 is available for use in commercial and industrial temperature ranges, packaged in a 28-pin SOIC. The HS3120 is available in commercial and military temperature ranges, packaged in a 28-pin side-brazed DIP. (MSB) Bit 1 9 22 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 9 10 18 19 (LSB) 11 BIT 12 20 VREF 4 CE HBE MBE LBE LDAC INPUT REGISTER 25 24 23 CONTROL LOGIC INPUT REGISTER INPUT REGISTER R 5 6 FB1 I 01 I 02 FB 4 FB 3 21 DAC REGISTER 12 BIT MDAC 7 1 R/2 R/2 3 SP7512, HS3120 28 VDD1 26 VDD2 27 GND 8 GND 2 LDTR Corporation 113 SIGNAL PROCESSING EXCELLENCE SPECIFICATIONS (Typical @ 25C, nominal power supply, VREF = +10V, unipolar, unless otherwise noted) PARAMETER DIGITAL INPUT Resolution 2-Quad, Unipolar Coding 4-Quad, Bipolar Coding Logic Compatibility MIN. TYP. MAX. UNITS Bits CONDITIONS 12 Binary & Comp. Binary Offset Binary CMOS, TTL The input coding is complementary binary if I02 is used. Digital input voltage must not exceed supply voltage or go below -0.5V ; "0" <0.8V; 2.4V < "1" VDD All strobes are level triggered. See Timing Diagram; GBD* All strobes are level triggered. See Timing Diagram; GBD* All strobes are level triggered. See Timing Diagram; GBD* Input Current Data Set-up Time Strobe Width Data Hold Time REFERENCE INPUT Voltage Range Input Impedance ANALOG OUTPUT Scale Factor Scale Factor Accuracy Output Leakage 1 250 250 0 A ns ns ns 4 62.5 25 12 187.5 V KOhms A/VREF % nA 0.4 10 Using the internal feedback resistor and an external op amp. At 25C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10C temperature increase. Output Capacitance COUT 1, all inputs high COUT 1, all inputs low COUT 2, all inputs high COUT 2, all inputs low STATIC PERFORMANCE Integral Linearity SP7512BN/KN, HS3120-2 Differential Linearity SP7512BN/KN, HS3120-2 Monotonicity SP7512BN/KN, HS3120-2 STABILITY Scale Factor Integral Linearity Differential Linearity STABILITY Monotonicity Temp. Range SP7512KN, HS3120C-_ SP7512BN HS3120B-_ 80 40 40 80 pF pF pF pF 0.015 0.024 Guaranteed to 12 bits 2 0.2 0.2 % FSR %FSR ppm FSR/C ppm FSR/C ppm FSR/C (TMIN to TMAX) Note 1 (TMIN to TMAX) 0 -40 -55 +70 +85 +125 C C C 114 Corporation SIGNAL PROCESSING EXCELLENCE SPECIFICATIONS (continued) (Typical @ 25C, nominal power supply, VREF = +10V, unipolar unless otherwise noted) PARAMETER MIN. TYP. MAX. DYNAMIC PERFORMANCE Digital Small Signal Settling 1.0 Full Scale Transition Settling 2.0 Reference Feedthrough Error @ 1kHz <1 @ 10kHz 2 Delay to output from Bits input 100 from LDAC 200 from CE 120 POWER SUPPLY (VDD) Operating Voltage +15 5% Voltage Range +5 +16 Current 2.5 Rejection Ratio 0.002 ENVIRONMENTAL AND MECHANICAL Operating Temperature SP7512K 0 +70 SP7512B -40 +85 HS3120-C 0 +70 HS3120-B -55 +125 HS3120-B/883 -55 +125 Storage Temperature -65 +150 Package SP7512_N 28-pin SOIC HS3120-C 28-pin Plastic DIP HS3120-B 28-pin Side-Brazed DIP Notes: 1. UNITS S S mV mV ns ns ns V V mA %/% CONDITIONS to 0.01% (strobed) (VREF = 20Vpp) Delay times are twice the amount shown at TA = +125 C specifications guaranteed C C C C C C Using the internal feedback resistor, output leakage current creates an offset, which doubles every 10C rise in temperature. Corporation 115 SIGNAL PROCESSING EXCELLENCE PIN ASSIGNMENTS Pin 1 - FB4 - Feedback Bipolar Operation Pin 2 - LDTR - Ladder Termination Pin 3 - FB3 - Feedback Bipolar Operation Pin 4 - VREF - Reference Voltage Input Pin 5 - FB1 - Feedback, Unipolar/Bipolar Pin 6 - IO1 - Current out into virtual ground Pin 7 - IO2 - Current out-complement of I01 Pin 8 - VSS - Ground, Analog and DAC Register Pin 9 - DB11 - MSB, Data Bit 1 Pin 10 - DB10 - Data Bit 2 Pin 11 - DB9 - Data Bit 3 Pin 12 - DB8 - Data Bit 4 Pin 13 - DB7 - Data Bit 5 Pin 14 - DB6 - Data Bit 6 Pin 15 - DB5 - Data Bit 7 Pin 16 - DB4 - Data Bit 8 Pin 17 - DB3 - Data Bit 9 Pin 18 - DB2 - Data Bit 10 Pin 19 - DB1 - Data Bit 11 Pin 20 - DB0 - LSB, Data Bit 12 Pin 21 - LDAC - Transfers data from input to DAC register; a logic "0" latches data into registers; a logic "1" allows data to change (transfer to) register. Pin 22 - CE - Chip Enable, active low Pin 23 - LBE - Bit 12 to Bit 9 Enable Pin 24 - MBE - Bit 8 to Bit 5 Enable Pin 25 - HBE - Bit 4 to Bit 1 Enable Pin 26 - VDD2 - Supply Analog and DAC Register Pin 27 - VSS1 - Ground input latches Pin 28 - VDD1 - Supply input latches NOTE: Pins 8 and 27, and pins 26 and 28 must be connected externally. FEATURES... The SP7512 and HS3120 are precision 12-bit multiplying DACs with internal two-stage input storage registers for easy interfacing with microprocessor busses. The DACs are implemented as a one-chip CMOS circuit with a resistor ladder network designed for 0.01% linearity without laser trimming. The input registers are sectioned into 3 segments of 4 bits each, all individually addressable. The DAC-register, following the input registers, is a parallel 12-bit register for holding the DAC data while the input registers are updated. Only the data held in the DAC register determines the analog output value of the converter. The SP7512 and HS3120 have been designed for great flexibility in connecting to bus-oriented systems. The 12 data inputs are organized into 3 independent addressable 4-bit input registers such that the DACs can be connected to either a 4, 8 or 16-bit data bus. The control logic of the DACs includes chip enable and latch enable inputs for flexible memory mapping. All controls are level-triggered to allow static or dynamic operation. A total of 5 output lines are provided on the DACs to allow unipolar and bipolar output connection with a minimum of external components. The feedback resistor is internal. The resistor ladder network termination is externally available, thus eliminating an external resistor for the 1 LSB offset in bipolar mode. The SP7512 is available for use in commercial and industrial temperature ranges, packaged in 400 V REF V DD2 V DD1 FB 1 I O1 DIGITAL INPUTS R OS A + V OUT +15V SP7512 LDTR FB 4 FB 3 I O2 CE HBE MBE LBE LDAC V SS V SS1 Figure 1. Unipolar Operation 116 Corporation SIGNAL PROCESSING EXCELLENCE -15V 20K V REF V DD2 400 +15V V DD1 FB1 +15V TRANSFER FUNCTION (N=12) BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT 111...111 100...001 100...000 V OUT ADJUSTMENT RANGE 0.2% 4M R OS1 A1 + 4K -VREF (1 - 2-N) -VREF (1/2 + 2-N) -VREF /2 -VREF (1/2 - 2-N) 0 -VREF (1 - 2 0 -(N - 1) ) -VREF (2 -(N - 1)) VREF (2 -(N - 1)) V REF DIGITAL INPUTS SP7512 I O1 FB 4 FB 3 I O2 LDTR N.C. N.C. 011...111 000...000 Table 1. Transfer Function 1K R OS2 A2 + 3K CE HBE MBE LBE LDAC V SS V SS1 V OUT1 A1, A2 , LF411ACN Figure 2. Bipolar Operation a 28-pin SOIC. The HS3120 is available in commercial and military temperature ranges, packaged in a 28-pin side-brazed DIP. For product processed and screened to the requirements of MIL-M-38510 and MIL-STD-883C, please consult the factory (HS3120B only). APPLICATIONS INFORMATION Unipolar Operation Figure 1 shows the interconnections for unipolar operation. Connect IO1 and FB1 as shown in diagram. Tie IO2 (Pin 7), FB3 (Pin 3), and FB4 (Pin 1) to Ground (Pin 8). To maintain specified linearity, external amplifiers must be zeroed. This is best done with VREF set to zero and, with the DAC register loaded with all bits at zero, adjust ROS for VOUT = 0V Bipolar Operation Figure 2 shows the interconnections for bipolar operation. Connect I O1, IO2 , FB1, FB3, FB4 as shown in diagram. Tie LDTR to I O2. To maintain specified linearity, external amplifiers must be zeroed. This is best done with VREF set to zero and, the DAC register loaded with 10...0 (MSB = 1), set ROS2 for VOUT1 = 0V. Then set ROS1 for VOUT = 0V. Grounding Connect all GND pins to system analog ground and tie this to digital ground. All unused input pins must be grounded. Corporation 117 SIGNAL PROCESSING EXCELLENCE TIMING INPUT DATA t3 CE t2 t1 LBE t3 t1 MBE t2 HBE LDAC t2 OUTPUT t4 TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED. t1: Data Setup Time, Time data must be stable before strobe (byte enable/ LDAC) goes to "0", t1 (min) = 250ns. t2: Strobe Width. t2 (min) = 250ns. (CE, LBE, MBE, HBE, LDAC). t3: Hold Time. Time data must be stable after strobe goes to "0", t3 = 0ns. t4: Delay from LDAC to Output, t4 = 200ns. NOTE: Minimum common active time for CE and any byte enable is 250ns. ORDERING INFORMATION Model .................................................................. Monotonicity ................................. Temperature Range ........................................ Package Double-Buffered 12-Bit Multiplying DAC SP7512BN ............................................................... 12-Bit ......................................... -40C to +85C ...................................... 28-pin, 0.3" SOIC SP7512KN ............................................................... 12-Bit .............................................. 0C to +70C ...................................... 28-pin, 0.3" SOIC HS3120C-2N ........................................................... 12-Bit .............................................. 0C to +70C ............................ 28-pin, 0.6" Plastic DIP HS3120C-2Q ........................................................... 12-Bit .............................................. 0C to +70C .................. 28-pin, 0.6" Side-Brazed DIP HS3120B-2Q ........................................................... 12-Bit ....................................... -55C to +125C .................. 28-pin, 0.6" Side-Brazed DIP HS3120B-2/883 ...................................................... 12-Bit ....................................... -55C to +125C .................. 28-pin, 0.6" Side-Brazed DIP 118 Corporation SIGNAL PROCESSING EXCELLENCE |
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